1. Field of the Invention
The solution according to an embodiment of the present invention regards the electronics field. More specifically, such solution relates to a non volatile memory device.
2. Discussion of the Related Art
A non volatile memory device is a type of memory capable of preserving stored information even in absence of any supply. Among the non-volatile memories presently available on the market, one of the most widespread is the memory of the flash type, simply referred to as flash memory.
A flash memory device is integrated on a chip of semiconductor material and includes one or more blocks, each formed in a respective insulated well (body). Each block comprises a matrix of memory cells with a plurality of rows and columns; the memory cells of each row are connected to a respective word line, while the memory cells of each column are connected to a respective bit line. Typically, each memory cell consists of a MOS transistor, having a floating gate insulated by means of a thin oxide layer.
Making reference to a single level memory, wherein each memory cell is adapted to store a single information bit, an unprogrammed memory cell has a reduced threshold voltage; therefore, when the memory cell is selected, a current flows through the respective bit line-stored bit corresponding to a logic value 1. The memory cell is programmed by injecting electric charge into its floating gate. In this condition, the memory cell has a high threshold voltage; therefore, when the memory cell is selected, no current flows through the respective bit line—stored bit corresponding to a logic value 0. The electric charge injection into the floating gate of a flash memory cell is carried out by a proper programming circuit, adapted to generate program current pulses exploiting voltages of values higher than the supply voltage of the device. Such voltages having values higher than the supply voltage are generated from the latter by a voltage booster circuit, such as a charge pump.
As known to skilled technicians, the current that may be provided by the programming circuit should not exceed a certain limit set by the voltage booster circuit, on penalty of a considerable degradation of the program operation duration, or, even worse, the occurrence of a device's malfunctioning. In order to comply with this limit, and not to incur in the above-mentioned drawbacks, it is preferable to set a maximum number of memory cells to be programmed at the same time—herein referred to as “internal degree of parallelism”. Since the values of the threshold voltages of the memory cells of a flash memory are not precisely known a priori—because of the tolerances of the manufacturing processes—the internal degree of parallelism is typically made to correspond to a number of memory cells capable of sinking a current that is sufficiently lower than the limit set by the voltage booster circuit. Particularly, the internal degree of parallelism is typically set in such a way that even programming one or more additional memory cells at the same time, the current sunk is, however, lower than the limit set by the voltage booster circuit, In other words, if correctly set, the internal degree of parallelism is to be intended as the “suggested maximum number of memory cells to be programmed at the same time” rather than the “maximum number of memory cells to be programmed at the same time at any cost”.
In order to solve this drawback, the solutions known in the art provide for sending program current pulses in parallel to a number of memory cells that is lower or equal to the abovementioned internal degree of parallelism. For example, if in a single level flash memory device the specifics provides for the addressing of 64 cells per each program operation, and the internal degree of parallelism is only equal to 16, the program operation is carried out in four subsequent phases, each of which relates to a respective group of 16 memory cells. Particularly, having to program a word formed by 64 bits b[63:0] in 64 respective addressed memory cells, the program operation would be carried out according to the following order:                1) programming of the bits b[15:0] in a first group of 16 cells by means of a first program current pulse;        2) programming of the bits b[31:16] in a second group of 16 cells by means of a second program current pulse;        3) programming of the bits b[47:32] in a third group of 16 cells by means of a third program current pulse, and        4) programming of the bits b[63:48] in a fourth group of 16 cells by means of a fourth program current pulse.        
Therefore, the presence of the constraint due to the internal degree of parallelism causes an increase of the total duration of the program operations. For example, presuming that the duration of each program current pulse is equal to 1 usec, in order to write all the 64 bits in the 64 addressed memory cells a total time of 4 usec will be necessary.
However, a program modality of this type is not efficient, as disclosed in the following.
Making reference again to the previous example, according to which a word formed by 64 bits b[63:0] has to be programmed in 64 respective memory cells of a flash memory having an internal degree of parallelism equal to 16, it is now supposed that such word is constituted by a number of 0's lower than 16, but distributed according to a scattered order. For example, such word may have the value 0x0FFFF0FFFFF0EEFF (wherein the prefix 0x means that the value of the word is expressed in hexadecimal), i.e., it includes a number of 0's equal to 14. Applying the previously described solution, the program operation would be carried out according to the following order:                1) programming of the bits b[15:0]=0xEEFF in a first group of 16 cells by means of a first program current pulse;        2) programming of the bits b[31:16]=0xFFF0 in a second group of 16 cells by means of a second program current pulse;        3) programming of the bits b[47:32]=0xFFF0 in a third group of 16 cells by means of a third program current pulse, and        4) programming of the bits b[63:48]=0x0FFF in a fourth group of 16 cells by means of a fourth program current pulse.        
Remembering that the memory cells actually subjected to programming, i.e., that actually receive the program current pulse, are those that have to store a 0, it can be noted that the four distinct program phases of the previously considered example may be redundant. Indeed, the overall number of bits of the word to be programmed having a 0 value is equal to 14, and thus is lower than the internal degree of parallelism (16). As a consequence, instead of carrying out four distinct program phases, the same result could be obtained with a single program phase, with a gain of 75% in terms of duration.